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Results: 1614

#	Item
951	Cache-Conscious Runtime Optimization for Ranking Ensembles Xun Tang, Xin Jin, Tao Yang Department of Computer Science, University of California Santa Barbara, CA 93106, USA Add to Reading List Source URL: www.cs.ucsb.edu Language: English - Date: 2014-06-02 10:18:37 Information CPU cache Central processing unit Computing Learning to rank Memory hierarchy Computer memory Cache Information science
952	Sanjeev N. Trika, p.5/5 SANJEEV N. TRIKA 6108 SE Sierra St., Hillsboro, OR[removed]Work tel: ([removed]Home tel: ([removed] Add to Reading List Source URL: www.strikaonline.info Language: English - Date: 2011-12-29 13:58:45 Intel Computer CPU cache Web3D Engineering 3D modeling Adobe Shockwave Player Computing Computer hardware Computer graphics
953	Performance Tradeoffs in Read-Optimized Databases Stavros Harizopoulos Velen Liang Daniel J. Abadi Add to Reading List Source URL: www.vldb.org Language: English - Date: 2006-09-05 10:22:30 Database management systems Computing Relational model Column-oriented DBMS Relational database CPU cache Extensible Storage Engine Cache Relation Data management Computer memory Data
954	Cache-Conscious Performance Optimization for Similarity Search Maha Alabduljalil, Xun Tang, Tao Yang Department of Computer Science University of California, Santa Barbara Add to Reading List Source URL: www.cs.ucsb.edu Language: English - Date: 2013-05-23 10:28:37 Central processing unit Computing Computer architecture CPU cache Cache-oblivious algorithm Memory hierarchy AMD 10h Microarchitecture Computer hardware Cache Computer memory
955	appears in: Proceedings of the ACM conference on High Performance Computer Architecture (HPCA3), February 1-5, 1997, San Antonio, TX. Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterizat Add to Reading List Source URL: www.cs.inf.ethz.ch Language: English - Date: 1999-08-06 17:43:38 Computer hardware Computer architecture Cray T3E Cray T3D CPU cache Cache Memory hierarchy Alpha 21164 Cray Computing Computer memory Supercomputers
956	Appears in: Proceedings of the 22nd International Symposium on Computer Architecture, June 21-25, 1995, Santa Marguerita di Ligure, Italy Optimizing Memory System Performance for Communication in Parallel Computers T. St Add to Reading List Source URL: www.cs.inf.ethz.ch Language: English - Date: 1997-01-16 13:50:31 Parallel computing Supercomputers Motherboard Cray T3D Throughput Direct memory access Cache Message Passing Interface CPU cache Computing Computer hardware Computer memory
957	Scalable Query Result Caching for Web Applications Charles Garrod [removed] Computer Science Dept. Carnegie Mellon University Add to Reading List Source URL: www.akamai.com Language: English - Date: 2009-08-27 01:02:40 Network performance Database caching Cross-platform software Proxy server CPU cache Content delivery network Apache HTTP Server Web cache Database management system Computing Cache Computer networking
958	Timing Anomalies in Multi-core Architectures due to the Interference on the Shared Resources Hardik Shah, Kai Huang and Alois Knoll Department of Informatics VI, Technical University Munich, 85748 Garching, Germany. {sha Add to Reading List Source URL: www6.in.tum.de Language: English - Date: 2013-12-19 04:43:37 CPU cache Latency Cache Worst-case execution time Synchronous dynamic random-access memory Parallel computing Conventional PCI Dynamic random-access memory Computer hardware Computer memory Computing
959	Microsoft PowerPoint - [removed] Add to Reading List Source URL: www.prace-ri.eu Language: English - Date: 2014-06-01 06:23:16 Partnership for Advanced Computing in Europe K computer CPU cache Computer hardware Computing Supercomputers
960	Cache Partitioning and Scheduling for Energy Optimization of Real-Time MPSoCs Gang Chen Kai Huang Add to Reading List Source URL: www6.in.tum.de Language: English - Date: 2013-05-15 08:23:19 Computing CPU cache Central processing unit Computer memory Microprocessors Electronics AMD 10h Multi-core processor Fast Fourier transform Computer hardware Cache Digital signal processing

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